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Summary
About the Role
About You
- Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
- 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
- 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM methodologies.
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) for building verification environments.
- Experience with revision control systems like Mercurial(Hg), Git or SVN.
- Experience with verification of ARM/RISC-V based sub-systems or SoCs.
- Experience in SV Assertions, Formal, Emulation along with functional verification.
- Experience in developing UVM based verification environments from scratch.
- Experience in architecting and implementing Design Verification infrastructure.
- Experience with high-speed interfaces like PCIe, RoCE, DDR, HBM, Ethernet.
- Experience with micro-architectural performance verification.
- Experience verifying GPU/CPU designs.
- Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs.
- Track record of 'first-pass success' in ASIC development cycles.
Benefits
- Competitive salary ranging from $142k to $203k per year.
- Bonus and equity options.
- Comprehensive benefits package.
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